The present invention relates to a ferroelectric transistor which contains two source/drain zones, a channel region and a gate electrode. A ferroelectric layerxe2x80x94that is to say, a layer of ferroelectric materialxe2x80x94is provided between the gate electrode and the channel region. The conductivity of the transistor is dependent on a polarization state of the layer of ferroelectric material. Such ferroelectric transistors are being studied in relation to non-volatile memories, among other applications. Two different polarization states of the ferroelectric layer are therein allocated to two different logic values of an item of digital information. Neural networks are another possibility for applying such ferroelectric transistors.
Because the ferroelectric material which is disposed on a surface of a semiconductor substrate exhibits poor boundary surface characteristics, which exert an adverse effect on the electrical characteristics of a ferroelectric transistor, it has been proposed that an intermediate layer be utilized in a ferroelectric transistor between the ferroelectric layer and the semiconductor material. This guarantees a sufficient boundary surface at the surface of the semiconductor substrate (see European Patent EP 0 566 585 B1 and H. N. Lee et al, Ext. Abst. Int. Conf. SSDM, Hamatsu 1997: pp. 382-83). Insulating stable oxides such as CeO2 or ZrO2 are typically utilized for the intermediate layer.
It is accordingly an object of the invention to provide a ferroelectric transistor which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a data retention storage time is longer than in the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a ferroelectric transistor. The transistor contains a semiconductor substrate, and two source/drain zones disposed in the semiconductor substrate. A space between the two source/drain zones defines a channel region having a surface. A dielectric intermediate layer containing an Al2O3 layer is disposed on the surface of the channel region. A ferroelectric layer is disposed above the dielectric intermediate layer and a gate electrode is disposed above the dielectric intermediate layer.
The data retention storage time refers to the time during which the polarization of the ferroelectric layer and with it the stored information remain saved.
The invention is thus based on the now described consideration. In a ferroelectric transistor as taught in the prior art, the ferroelectric layer is disposed between the intermediate layer and the gate electrode. For purposes of compensating the remanent electric field that is brought about by the polarization in the ferroelectric layer, compensation charges occur on the gate electrode, on one hand, and in the semiconductor substrate in the region of the channel of the transistor, on the other hand.
The compensation charges located in the semiconductor substrate in the region of the channel of the transistor can be injected by thermically excited charge injection (i.e. Schottky emission) into the conduction band of the insulator from which the intermediate layer is formed, and can thereby reach the boundary surface between the intermediate layer and the ferroelectric layer. If the transistor is subsequently driven under the opposite polarity, the charges compensate the electric field brought about by the polarization of the ferroelectric layer. As a result, the underlying transistor channel can no longer be controlled by the polarization of the ferroelectric layer. The data storage time of the ferroelectric transistor is thus shortened.
In the inventive ferroelectric transistor, this effect is prevented in that the first dielectric intermediate layer contains Al2O3. Al2O3 has a band gap larger than 8 eV, compared to approximately 4 eV for CeO2 or ZrO2, which are utilized as the intermediate layer in conventional ferroelectric transistors. In the inventive ferroelectric transistor, the thermically excited charge injection is precluded due to the substantially higher potential barriers in Al2O3. Charge carriers can only be injected into the first dielectric intermediate layer when they tunnel through the forbidden band of the Al2O3. The tunnel mechanism is several orders of magnitude smaller than the thermically excited charge injection in conventional ferroelectric transistors.
If the first dielectric intermediate layer is 5 nm thick, then 4 volts would have to drop across the first dielectric intermediate layer in order for a charge transport by Fowler-Nordheim tunneling from the channel region of the transistor into the first dielectric intermediate layer to set in. Given a realistic mode of operation, at most 0.1 to 1.5 volts drop across the first dielectric intermediate layer. Leakage currents from the channel region into the first dielectric intermediate layer are thus actively suppressed.
In accordance with an added feature of the invention, the dielectric intermediate layer has a thickness of between 5 and 20 nm.
In accordance with an additional feature of the invention, the dielectric intermediate layer is formed of multiple layers. The dielectric intermediate layer further contains SiO2 or Si3N4.
Preferably, a second dielectric intermediate layer is disposed between the ferroelectric layer and the gate electrode. With the aid of the second dielectric intermediate layer, leakage currents of compensation charges on the gate electrode are suppressed to the boundary surface between the ferroelectric layer and the first dielectric intermediate layer by the ferroelectric layer. The leakage currents can also reduce the data storage time of the ferroelectric transistor, because they compensate the electric field caused by the polarization of the ferroelectric layer given repoling of the transistor. As a result, the underlying transistor channel can no longer be controlled by the polarization of the ferroelectric layer. In this embodiment, because the gate electrode does not adjoin the ferroelectric layer directly but rather is isolated from it by the second dielectric intermediate layer, leakage currents from the gate electrode are suppressed by the ferroelectric layer. This improves the functionality of the ferroelectric transistor and lengthens the data storage time.
In accordance with another feature of the invention, the second dielectric intermediate layer is formed of Al2O3, CeO2 or ZrO2, and has a thickness between 2 and 20 nm. Furthermore, the second dielectric intermediate layer is formed of multiple layers and additionally contains SiO2 or Si3N4.
In order to change the polarization of the ferroelectric layer of the ferroelectric transistor, a voltage is usually applied between the semiconductor substrate and the gate electrode. The first dielectric intermediate dielectric layer, the ferroelectric layer, and the second dielectric intermediate layer therein represent a series circuit of capacitances. The first and second dielectric intermediate layers are therefore preferably made of a material with a sufficiently large dielectricity constant that the capacitances of the first dielectric intermediate layer and the second dielectric intermediate layer exert optimally little electrical influence on the ferroelectric transistor. Al2O3 has a dielectricity constant between 9 and 12, so that this condition is satisfied for the first dielectric intermediate layer.
It is within the scope of the invention to form the second dielectric intermediate layer from Al2O3, CeO2 or ZrO2. The first dielectric intermediate layer and the second dielectric intermediate layer can be formed from the same material or different materials. All materials with a large dielectric constant are particularly well suited. Utilizing Al2O3 for the second dielectric intermediate layer is advantageous in that a thermically excited charge injection (or Schottky emission) from the gate electrode into the ferroelectric layer is suppressed.
The first and/or second dielectric intermediate layers can also be formed as multi-layers if this is technically expedient. The first and/or second dielectric intermediate layers can additionally contain either Si3N4 or SiO2.
In order to completely rule out leakage currents through the ferroelectric layer, it is advantageous also to isolate the ferroelectric layer laterally by dielectric flank coverings, in addition to the first and second dielectric intermediate layers. Al2O3, CeO2 or ZrO2 are likewise suitable for the dielectric flank coverings.
In the region of the ferroelectric transistor, the semiconductor substrate contains at least one material that is suitable for realizing an electronic circuit component. It preferably contains silicon and/or germanium. In particular, a monocrystalline silicon wafer or silicon-on-insulator (SOI) substrate is a suitable semiconductor substrate.
All ferroelectric materials which are suitable for utilization in a ferroelectric transistor are suitable materials for the ferroelectric layer. It preferably contains silicon and/or geranium. Specifically, the ferroelectric layer contains SBT (SrBi2Ta2O9), PZT (PbZrxT1xe2x88x92xO2), LiNbO3 or BMF (BaMgF4).
Doped polysilicon, platinum or tungsten are particularly suitable for the gate electrode. Beyond this, the gate electrode can be realized as a multi-layered structure. In particular, a diode structure can be realized in such a multi-layered structure.
The ferroelectric transistor can be realized as either a p or n channel transistor. It can be realized as either an enhancement transistor or a depletion transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claims. Although the invention is illustrated and described herein as embodied in a ferroelectric transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.